Validation/Verification (UVM, Coverage, Agentic), Staff Engineer

Validation/Verification (UVM, Coverage, Agentic), Staff Engineer

General Information

Job Title

Validation/Verification (UVM, Coverage, Agentic), Staff Engineer

Job ID

17517

Country

India

City

Hyderabad

Date Posted

15-May-2026

Job Category

Engineering

Job Subcategory

Validation / Verification Eng

Hire Type

Employee

Remote Eligible

No

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in verification, closing coverage on complex IP and SoC designs, and you know that the hardest part is not writing the tests but knowing when you are actually done. You understand the difference between hitting a metric and truly verifying a design, and you have debugged enough corner cases to recognize when something does not add up, whether it came from a human or an AI. You are curious about how AI can change verification work, not because it is trendy but because you have seen the manual grind of coverage closure and you want better tools. You do not blindly trust AI outputs. You validate them, push back when they miss the mark, and help refine the systems so they get smarter. You think of AI as a coworker you are training, not a magic box. You care about knowledge quality. You have seen what happens when verification artifacts are poorly documented or inconsistently tagged, and you take ownership of making sure the information you create can actually be reused. At Synopsys, you will work on verification workflows that are being transformed by AI, and what you validate, curate, and teach will shape how the next generation of verification gets done.

Drive end-to-end verification closure on complex IP and SoC designs, including functional, code, and scenario coverage using UVM, SystemVerilog Assertions, and simulation tools like VCS and Verdi Define coverage strategies, identify gaps, and use AI-assisted tools to accelerate test generation, debug, and convergence while independently validating all outputs for correctness Collaborate with AI agents and tools for testbench generation, coverage analysis, debug assistance, and report generation, actively evaluating and refining what they produce Own the quality and structure of verification artifacts, ensuring test plans, debug logs, and reports are well-tagged, contextualized, and consumable by AI systems Provide structured feedback to AI and tool development teams to improve model accuracy, usability, and trustworthiness in verification workflows Pilot and benchmark AI-based verification solutions, measuring their impact on productivity, quality, and coverage closure timelines Contribute to building self-improving knowledge systems that evolve with verification data and enable scalable reuse across global teams The Impact You Will Have Accelerate coverage closure cycles and reduce time to signoff by integrating AI-assisted methodologies into verification workflows Increase trust and adoption of AI tools across verification teams by validating outputs and demonstrating where they add real value Improve the quality and completeness of verification outcomes through domain-driven insights and rigorous validation practices Enable scalable, reusable knowledge systems that enhance organizational learning and reduce redundant work across projects Help shape the transition to agentic, autonomous verification ecosystems by defining what good AI collaboration looks like in practice Influence verification strategy and tooling