Systems and Test Integration Engineer - FPGA Integration & Verification

Basic Qualifications Bachelor's degree in Systems Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Job Description

ROLE AND POSITION OBJECTIVES: As a Systems and Test Integration Engineer - FPGA Integration & Verification, on the GDMS TIDES team, you will do two related kinds of FPGA work that support spacecraft payload development. You will design FPGAs from architecture through implementation for the shared test infrastructure. These are FPGAs that handle interface bridging between the test equipment and the unit-under-test, real-time functions like packet timestamping and precision command scheduling, and other test-support work. You will also bring up FPGA interfaces on real hardware, maturing the development platform and enabling test software infrastructure to be built. This is FPGA engineering for the Hardware Development Environment (HDE), a shared engineering platform that all spacecraft payload programs at GDMS build on. In this role you will own FPGA features end to end, from microarchitecture through lab bring-up, and grow toward independently architecting test FPGAs. Your work directly enables faster hardware bring-up, more reliable integration testing, and a smoother path from development to design verification to flight readiness. You will contribute to FPGA architecture decisions, write RTL, establish interface communications in the lab, and help shape how the HDE evolves, all in a mission-focused environment. Preferred Skills & Experience:

3+ years of experience in FPGA design, integration, and hardware bring-up, spanning microarchitecture definition through hardware integration Proficiency in SystemVerilog and/or VHDL for RTL design Comfortable writing designer-level testbenches to stimulate and validate your own submodules in simulation before hardware Ability to work at the systems level: understanding how the surrounding system drives test FPGA requirements and how the test FPGA fits into the larger test-and-integration picture Hands-on experience designing and integrating FPGA interfaces such as Ethernet, JESD204B/C, SPI, etc. Proficiency in synchronous and asynchronous design principles, timing closure, and constraint generation Experience with FPGA vendor toolchains (Xilinx/AMD Vivado, Lattice Diamond/Radiant, or equivalent) Hands-on experience integrating FPGA interfaces in a lab environment (JTAG, oscilloscopes, protocol analyzers, debugging on real hardware) Proficiency in scripting languages such as Linux shell scripts, Python, and Tcl Experience with Git-based version control workflows (branching strategies, merge requests, code review) Experience working in Linux environments (RHEL, Ubuntu); comfortable at the command line Familiarity with CI/CD platforms (GitLab CI or equivalent) for FPGA build and release automation Experience with computer networking (Ethernet configuration, subnets, routing) Familiarity with agile/scrum workflows and sprint-based delivery Experience deriving test FPGA requirements from system-level needs: working with hardware, systems, and test engineers to define what a test FPGA has to do, not just implementing a fully-architected design

Design FPGAs for the shared test infrastructure, including interface translation between the unit under test and the test system, and real-time functions like packet