Principal Hardware Application Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact This is a hands-on, customer-facing engineering role based in Taiwan. You will work closely with customers hardware teams, Marvell's global engineering organization, and cross-functional teams including SI/PI, PSE, and software AE. What You Can Expect Customer design engagement: Serve as the primary hardware technical focal for strategic accounts. Drive design-in activities from schematic review through board bring-up, EDVT, and mass production. * Schematic and layout review: Review customer PCB schematics and layout files for Marvell DC switch platforms. Provide design guidance on component selection, power sequencing, clock distribution, and high-speed signal routing. * SI/PI analysis: Perform or coordinate signal integrity and power integrity simulations (pre- and post-layout) for high-speed Ethernet interfaces at 800G, 1.6T, and beyond. Evaluate channel performance, SerDes tuning (Tx EQ / Rx CTLE), and PAM4 link margin. * Board bring-up and debug: Support hardware bring-up at customer sites and in Marvell's Taipei lab. Debug L1 issues including SerDes link training, power integrity, thermal, and interface failures. * Design documentation: Author and review hardware design guides, application notes, schematic checklists, and layout guidelines for internal and external use. * Cross-functional collaboration: Join-in EE/ME/SI/PI design reviews with Marvell's global hardware engineering team. Represent customer requirements and feed back design insights to silicon and platform teams. * Technology exploration: Ramp up knowledge on next-generation interconnect technologies including UALink, ESUN, CPO (Co-Packaged Optics), and 224G SerDes. Contribute to internal training and knowledge-sharing forums. * Supplier chain engagement: Leverage Taiwan's comprehensive supply chain ecosystem — PCB materials, thermal solutions, power components, connectors, and cabling — to optimize platform designs.

Basic Qualifications: Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related field 8+ years of experience in hardware design or hardware application engineering for high-speed networking or data center systems Proficiency in EE design tools: schematic capture (e.g., Cadence OrCAD, Mentor PADS, or equivalent) and PCB layout review (e.g., Cadence Allegro or equivalent) Solid knowledge of signal integrity (SI) principles for high-speed differential interfaces: understanding of channel loss, eye diagram analysis, SerDes Tx/Rx equalization, and PAM4 link budget Familiarity with power integrity (PI) concepts: PDN design, AC/DC simulation, decoupling strategy, and power sequencing Experience supporting customers through the hardware design cycle: schematic review, layout review, bring-up, and EDVT Strong communication skills — able to present technical findings clearly to both engineering teams and customer stakeholders Proactive, self-driven working style with the ability to manage multiple customer engagements in parallel Preferred Qualifications: Hands-on experience with DC switch or high-speed Ethernet platforms (e.g., 400G, 800G, 1.6T switch designs) Familiarity with Marvell Teralynx (TL7, TL10, T100) or equivalent DC switch silicon Experience with SI/PI simulation tools (e.g., Sigrity, Ansys SIwave, HFSS, PowerDC or equivalent) Knowledge of next-generation interconnect technologies: UALink, ESUN, CPO,