Senior Silicon Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the DFX (Design for Test & Debug) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.   We are looking for a experience Silicon Design for Test (DFT) Engineer to join the team.   #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: Own block-level DFT architecture, specifications, and implementation for logic and memory test solutions. Drive DFT timing closure and signoff across Scan, MBIST, LBIST, IJTAG, and in-system test modes. Develop and maintain DFT STA constraints, timing exceptions, and signoff methodologies throughout the design cycle. Ensure robust timing of DFT infrastructure, including test clocks, OCCs, clock muxing, and clock-gating architecture. Analyze and resolve DFT timing issues in complex multi-clock and low-power designs using advanced STA techniques. Develop automation and AI-assisted workflows to improve DFT timing analysis, signoff efficiency, and productivity. Support post-silicon debug by correlating timing analysis with silicon test results and driving root-cause resolution. Provide technical leadership and collaborate across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams to deliver high-quality silicon.

Required Qualifications: BS, MS, or Ph.D. in Electrical Engineering, or Computer Engineering with over 5 years of experience between the fields of DFT & STA. Knowledge about industry standard practice in Design for Test - ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time.

Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits. Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax. Experience in constraint development & timing closure for DFT modes – includes deep analysis of timing paths to identify key issues through Primetime Static Timing Analysis (STA), Clock-Domain-Crossing (CDC), and Reset-Domain-Crossing (RDC). Ability to automate generation of SDC’s and also utilize EDA tool