Design Verification Engineer

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Design Verification Engineer

Santa Clara

California

8/6/26

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regression runs, analyze results, and contribute to continuous improvements Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains Document test environments, testplans, and results for internal and external reviews

Mandatory Skills: VLSI HVL Verification

.   Experience: 3-5 Years

.   The expected compensation for this role ranges from $45,000 to $121,000 .   Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant