Layout Design, Sr Engineer

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills—both verbal and written—enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything. What You’ll Be Doing: Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement. The Impact You Will Have: Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products. Ensuring robust and reliable IP performance through meticulous layout design and physical verification. Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more. Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader. Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements. Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization. Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally. What You’ll Need: BTech/MTech degree in Electronics, Electrical, or related engineering discipline. 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below). Expertise in DRC, LVS,