Staff Engineer- RTL Design
Marvell Technology
- Location
- Bangalore
- Work model
- On-Site
- Level
- Staff
- Posted
- 23h ago
Skills
About this role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Work with the Architecture team as a design-team leader or member, to shape the micro-architecture of the chip. Write specifications for the relevant block, micro-architecture of one or more block Implement a specification using RTL coding techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug. Work with the post-silicon validation teams in qualifying the device for production Work with the project manager to scope and assign tasks, including mentoring less experienced engineers Work with multiple design centers and design groups to shape future methodology Work with software teams to ensure the product meets all software use cases Provide technical guidance and mentoring to junior engineers What We're Looking For Bachelor’s degree, Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields and 4+ years of related professional experience. Experience in Micro-architecture for the complex Custom SoC/ASIC products focusing in any one/more areas: Hardware accelertors, Embedded Processors, and/or general purpose microprocessors. Excellent Logic design and debug skills; proficiency in protocols like PCIe/CXL/D2D/UCIe/USB; knowledgeable in bus protocols like AHB/AXI/I2C/UART RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification. Design knowledge of one/more industry-standard bus interfaces (PCIe, SPI, USB, etc.) and memory interfaces (DDR2, DDR3, etc.) are a plus. Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a must. Knowledge of scripting languages such as Perl, Tcl, and UNIX shell, etc. is a plus. Self-motivated individual who bring positive impacts to the team and organization Team leadership, interpersonal skills and excellent verbal and written communication skills. Problem solving and debugging skills. Can lead through ambiguity and change management. Team player who provides appropriate feedback to management & team members. Ability to operate in a fast-paced environment while creating an environment where teammates feel appreciated & feel recognized for their contributions. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.