High Speed IP PHY Applications Principal Engineer / Manager

High Speed IP PHY Applications Principal Engineer / Manager

General Information

Job Title

High Speed IP PHY Applications Principal Engineer / Manager

Job ID

17697

Country

Korea, Republic of

City

Yongin-Si

Date Posted

02-Jun-2026

Job Category

Engineering

Job Subcategory

Applications Engineering

Hire Type

Employee

Remote Eligible

No

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in ASIC design and verification, and somewhere along the way you realized that the most satisfying part of the work is not just getting the design right, it is helping someone else get their design right. You enjoy isolating root causes, asking the right questions, and driving issues to closure under tapeout pressure. You can work across the ASIC flow (synthesis, CDC, STA constraints, bring-up debug) and communicate clearly with both architects and implementation teams.

Provide technical support to customers integrating DesignWare USB Mixed Signal PHY IP as the primary focus, from initial integration through silicon bring-up and debug Troubleshoot customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing in USB PHY and SoC integration contexts Guide customers through USB 2.0, USB 3.x, and Type-C implementation considerations and design tradeoffs, and help define bring-up and debug plans that reduce time-to-silicon Collaborate closely with the Korea AE team and Synopsys R&D and product teams to escalate complex issues, drive root-cause analysis, and ensure timely closure during critical milestones In addition to USB, contribute to customer support coverage for other high-speed interface PHY IP in collaboration with colleagues, leveraging similar integration and debug fundamentals (e.g., MIPI, PCIe, HDMI, etc.; excluding DDR) Deliver technical presentations and integration best practices to customer engineering teams during design reviews and key program checkpoints Travel occasionally to customer sites across Korea and the region to support critical milestones The Impact You Will Have Enable customer success on high-stakes tapeouts by resolving USB PHY integration issues that would otherwise delay schedules Reduce time-to-silicon by providing clear, actionable guidance during integration, constraints closure, and silicon bring-up Build deep technical relationships with leading semiconductor companies in Korea as their trusted advisor Shape future IP releases by channeling real customer pain points back into the product team Expand Synopsys footprint in customer accounts through technical depth, responsiveness, and cross-team collaboration What You'll Need Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10 to 20+ years of ASIC design, verification, or SoC integration experience Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing Ability to work independently and drive ambiguous, customer-driven issues to resolution Excellent communication skills in Korean and English, able to explain complex concepts clearly USB 2.0, USB 3.x, Type-C, or USB PHY integration experience is a strong plus Broader high-speed interface background (e.g., MIPI, PCIe, HDMI) is a plus and helps with collaborative cross-IP support coverage Willingness to travel occasionally within Korea and the region Who You Are You can take a vague customer complaint and within two