STA Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING   At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.   Together, we advance your career.    PMTS SILICON DESIGN ENGINEER     THE ROLE:   We are seeking an experienced  Full Chip SoC Timing Lead  with  15+ years of industry experience  in  ASIC/SoC design implementation and timing closure . The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This role requires deep expertise in  STA, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaboration  with RTL, PD, CTS, DFT, power, and signoff teams.     THE PERSON:   You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Lead  full-chip timing closure  for complex SoC/ASIC designs across all modes and corners. Own and drive  timing signoff  from synthesis to final tapeout. Develop, validate, and maintain  timing constraints  including SDC for full-chip and block-level integration. Perform and review  static timing analysis (STA)  for setup, hold, recovery, removal, clock gating, and async paths. Drive  MMMC timing methodology  and ensure robust timing convergence across PVT corners. Work closely with  physical design teams  on floorplanning, placement, CTS, routing, and post-route timing optimization. Analyze and resolve  timing violations  related to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects. Lead  timing ECO strategies  and execute closure with minimal impact to power, area, and performance. Collaborate with  RTL/design teams  to identify architectural or logic changes required for timing improvement. Coordinate with  IP/block owners  for timing budgeting, interface timing closure, and hierarchical timing signoff. Ensure signoff quality using industry-standard tools and methodologies. Drive correlation between  implementation timing  and  signoff timing . Lead tapeout readiness reviews and provide timing risk assessment to program leadership. Mentor junior engineers and define best practices for timing methodology and closure.

Bachelor’s or Master’s degree in  Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering . 15+ years  of hands-on experience in  ASIC/SoC timing analysis and timing closure . Strong expertise in  full-chip STA and timing signoff  for large-scale SoCs. Proven experience in  advanced technology nodes  (such as  7nm, 5nm, 3nm  or similar). Strong knowledge of  synthesis, place-and-route, extraction, and signoff flows . Experience with  timing budgeting and hierarchical/full-chip integration . Solid understanding of  clocking architecture , CDC implications, and timing exception handling. Ability to debug complex timing issues and drive closure under aggressive schedule targets. Strong communication, stakeholder management, and leadership skills. #LI-AB1 Benefits offered are described:  AMD benefits at a