EDA Tools SW Engineer

Job Description: At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DTP cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs. The Technical Lead position within the Design Enablement (DTP) organization of Intel Foundry is a Design Enablement Applications and Support Technical Lead position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions. Lead and develop a high-performing engineering team by setting priorities, driving execution across organizational boundaries, and fostering an inclusive and collaborative work environment. Provide technical leadership, mentoring, and coaching while ensuring delivery of engineering objectives aligned with schedule, quality, and cost targets. Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution through sound technical judgment. Promote team values, accountability, and continuous improvement while guiding employee development, performance, and productivity. Exercise independent judgment in addressing complex challenges that may require deviation from standard practices. Required behavior traits Strong customer focus with a commitment to responsive support and issue resolution. Demonstrated analytical problem-solving skills and ability to collaborate across organizations. Proven leadership, influencing, and communication skills, with experience driving results through cross-functional teams.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

BS degree with 10+ years of experience or MS degree with 8+ years of experience or PhD degree with 6+ years of experience in Electrical Engineer or Computer Engineering or related field. 6+ years of experience in two or more of the following: Technical management or lead experience mentoring or leading medium sized teams. Experience with Test chip physical verification and tape-in Intel and/or external foundry process technology knowledge in advance nodes. Industry direct experience and in-depth knowledge to support customers in ASIC/Physical Design and/or Physical Verification/runsets, in advanced technology nodes, or EDA tools. Experience with technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.

Experience in advanced-node semiconductor design and verification methodologies. Experience with customers and stakeholders to resolve complex design and technology challenges.            Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual