Director of Design Verification

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Title: Director of Design Verification

We are seeking a seasoned Director of Design Verification with 15+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.

• Own and drive the end-to-end verification methodology for a specific product line.

• Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.

• Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.

• Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.

• Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.

• Represent verification in executive reviews, customer engagements, and industry forums.

• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).

• 15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.

• Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.

• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.

• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

• Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).

• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.

• Strong background in writing assertions, cover properties, and analyzing coverage data.

• Experience in developing VIP abstraction layers to simplify and scale verification deployments.

• Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.

• Experience with buffering, queuing, and QoS in complex NoC-based SoCs.

• System-level performance analysis on switching fabrics.

• Familiarity