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Hardware System Architecture Fellow - AI & Data Center Networking

AMD

Santa Clara, CaliforniaFellowshipStaff
Sign in to applyVerified 1h ago
Location
Santa Clara, California
Employment
Fellowship
Work model
On-Site
Level
Staff

About this role

WHAT YOU DO AT AMD CHANGES EVERYTHING   At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.   Together, we advance your career.

THE ROLE

The Hardware System Architecture Fellow – AI & Data Center Networking is the highest‑impact individual contributor responsible for defining and driving end‑to‑end hardware system architecture for AMD’s next‑generation AI and data center networking platforms.   This role provides system‑level technical leadership, spanning architecture definition, cross‑domain trade‑offs, and resolution of the most complex hardware challenges across AI‑NICs, DPUs, switches, and rack‑scale networking solutions. THE PERSON: The Fellow operates with enterprise‑scale technical authority, shaping multi‑generation system architectures and influencing execution across ASIC, packaging, board, optics, power, thermal, mechanical, firmware, and manufacturing domains, without direct people management responsibility.   The ideal candidate is a recognized technical leader with deep system expertise, strong architectural judgment, and the ability to influence across organizations through credibility, clarity, and technical depth.

KEY RESPONSIBILITIES

System Architecture & Technical Vision Define system‑level architecture for AI scale‑out and scale‑up networking platforms, translating product and business requirements into robust, scalable hardware solutions. Drive architectural decisions across chip‑to‑system boundaries, including interconnect topology, board and system partitioning, power delivery strategy, signal integrity constraints, and platform extensibility. Lead early‑phase system feasibility analysis, proactively identifying risks, trade‑offs, and technology inflection points. Cross‑Domain Technical Leadership Serve as the primary technical authority for system‑level challenges spanning ASIC, packaging, board design, optics, power, thermal, and mechanical integration. Resolve the most complex bring‑up, validation, and field issues, synthesizing cross‑domain data to drive root‑cause closure and architectural improvements. Ensure architectural intent is preserved through design, validation, and production ramp.   Methodology & Engineering Standards Establish and evolve system architecture best practices, review frameworks, and decision‑making methodologies across NTSG. Define standardized architecture review and system validation flows to improve predictability, reuse, and overall execution quality. Champion a disciplined system‑level engineering mindset across hardware development organizations.   Influence, Mentorship & Technical Leadership Influence senior engineers, architects, and leaders across organizations through technical depth and credibility, rather than authority. Mentor Principal and PMTS engineers on system architecture, trade‑off analysis, and Fellow‑level technical growth. Represent NTSG in cross‑organization architecture reviews and Fellow‑level technical forums.   Strategic Impact Shape multi‑generation system and platform roadmaps aligned with AMD’s AI networking strategy. Anticipate and lead architectural transitions in bandwidth scaling, optical adoption, power density, and rack‑level integration. Guide organizations through major architectural shifts while minimizing execution risk.   QUALIFICATIONS:

Hardware System Architecture Fellow - AI & Data Center Networking at AMD, Santa Clara, California | Yoinka