Server Performance Architect-CPU
AMD
- Location
- Austin, Texas
- Employment
- Full Time
- Work model
- On-Site
- Level
- Mid
Skills
About this role
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
AMD is looking for an outstanding technical contributor to help architect, validate & optimize performance of new features thru full chip simulation & emulation platforms for AMD-based next-generation servers . THE PERSON: As a passionate and dedicated Server Systems Performance Architect in the Server Performance Group , you will identify new opportunities to optimize server silicon for throughput and latency by identifying opportunities across all parts of silicon micro architecture and design spanning CPU, Data Fabric, Memory subsystem and IO. You will validate and analyze performance of various design features in presilcon design env and correlate the profiling data with AMD performance model and eventually AMD silicon. You will quantify and isolate performance bottlenecks, and share the insights to help new drive features into the next generation of server CPUs. The ideal candidate is expected to be well informed on latest trends in server design and verification, have a well rounded understanding of performance requirements for server market and be able to quickly ascertain, in a data-driven manner, how next generation server CPUs and platforms should be engineered to support those needs KEY RESPONSIBILITIES :
Team
Leadership Lead and mentor a high-performing team of performance verification engineers. Foster a culture of innovation, technical rigor, and continuous improvement. Provide strategic direction across multiple concurrent verification programs. Program Leadership Define and execute the performance verification strategy for high-performance x86 CPU cores. Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs. Ensure timely delivery of simulation/emulation results, and optimization feedback loops. Performance Analysis & Correlation Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency. Capability to debug performance outliers through Performance Monitoring Counters (PMC). Drive correlation between RTL and performance models, ensuring architectural intent is met. Analyze performance bottlenecks using simulation, emulation, and silicon data. Toolchain & Methodology Build and maintain scalable, modular performance verification infrastructure. Lead emulation-based performance setup and debug, enabling early performance validation. Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools. Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals. AI-Driven Infrastructure Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements. Leverage data-driven techniques to optimize verification coverage and reduce debug cycles. Cross-Functional Collaboration Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met. Influence design decisions through data-backed performance insights. Stakeholder Management Align verification goals with business and product roadmaps. Communicate performance status, risks,