Sr. Staff Hardware Design Engineer, SoC/SIP
Qualcomm
- Location
- San Diego, California, United States of America; Austin, Texas, United States of America
- Work model
- On-Site
- Level
- Staff
- H-1B history
- 22 approvals (FY2023)
- Posted
- 2d ago
Skills
About this role
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The Qualcomm Data Center AI Hardware Engineering team designs and develops motherboards/add in cards/modules for Qualcomm new AI System On Chip (SoC)/System In Package (SIP). Primary responsibilities include working with cross functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) for execution of projects from concept to production. Support rack level design and integration of cards, servers and networking switches. Join a world-class, multidisciplinary team that is shaping the future of AI infrastructure. You will be working alongside industry-leading experts across the entire AI infrastructure stack—from silicon, systems architecture, networking, and distributed computing to machine learning platforms and large-scale AI deployment. Our collaborative and fast-paced environment offers unparalleled opportunities for learning, innovation, and professional growth, empowering you to solve some of the most challenging problems in the industry.
Responsibilities
Lead schematics design, PCB layouts, design reviews, component selections, mechanical and thermal designs, and develop test plans. Co-develop functional specifications for systems, cards, sub-systems, and rack-level architectures. Collaborate with internal teams and ODMs to develop and support customer-specific hardware and system requirements. Facilitate consensus on technical trade-offs at hardware, software, and chip design levels. Support architecture and card designs including accelerator SoCs, memory, I/O, power delivery, electrical/mechanical integration, and PCB definition/design. Participate in the design and development of rack-level inference solutions, ensuring alignment with customer requirements and system-level performance goals. Resolve architecture and design issues across system, card, and rack levels. Assist in the bring-up and debugging of hardware systems, cards, and rack-level configurations. Provide technical oversight of factory and manufacturing processes, ensuring quality and consistency across rack-level deployments. Contribute to writing Statements of Work (SOWs) and ODM product requirements; drive technical milestones and deliverables. Coordinate across multiple development sites, including Qualcomm locations and ODM/JDM partners in Taiwan and internationally. Travel to development and customer sites as needed to support rack-level solution deployment and validation. Influence and communicate technical recommendations across disciplines and geographic locations. Coordinate and deliver technical training for ODMs, with a focus on rack-level system integration and deployment. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
REQUIRED EXPERIENCE
System/card/rack-level development, including architecture, design, validation, and deployment of enterprise-class hardware platforms. Rack-Level Expertise: Proven experience in rack-level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules. Familiarity with rack-scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards. Experience with rack-level diagnostics and bring-up, including debug of interconnects, signal integrity across long traces/cables, and system-level validation. Understanding of rack-level mechanical constraints, EMI shielding, and compliance with data