Hardware Engineering Technical Leader

The application window is expected to close on: 08/20/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Acacia, a Cisco company, is a market leader in high-speed coherent optical transceivers and a pioneer in coherent pluggable transceiver technology. Its coherent solutions are deployed by every major hyperscale cloud provider, enabling data center interconnects spanning from a few kilometers to thousands of kilometers, as well as long-haul and submarine networks. The rapid growth of AI infrastructure has significantly increased demand for Acacia’s coherent transceivers. Beyond terrestrial networking, Acacia’s technology is also being adopted for space applications and is expected to play an increasing role within data centers as interconnect speeds continue to scale. In addition to its leadership in coherent optics, Acacia is expanding into the PAM4 client optics market and is well positioned to become a leading provider of PAM4 solutions, including next-generation 1.6T PAM4 DSPs.

As a Senior Photonics Packaging Engineer on the Acacia Packaging Engineering team, you will join a multidisciplinary group of optical, mechanical, electrical, and manufacturing engineers focused on developing next-generation optical communication products. In this role, you will work closely with Acacia's Silicon Photonics (PIC) development team to drive new product designs and collaborate with Product Engineering and Quality teams to ensure seamless transfer into manufacturing. You will play a critical role in the design, development, qualification, and production ramp of advanced transceivers that leverage silicon photonics and ground breaking DSP technology. The position also involves resolving technical challenges encountered during prototyping, product qualification, and high-volume manufacturing while driving solutions that deliver exceptional performance, reliability, cost efficiency, scalability, and manufacturability. Additional responsibilities include: •    Lead technical ownership of optical transceiver assembly process development, with a focus on silicon photonics packaging using advanced manufacturing technologies. •    Develop high-volume, highly automated, and cost-effective manufacturing processes that meet performance, scalability, reliability, and cost objectives. •    Drive the development and optimization of 2D/2.5D/3D wafer-level packaging processes, including flip-chip wafer-level bonding, Cu pillar (CuP), C3/C4 bumping, and Through-Silicon Via (TSV) integration. •    Design and implement Design of Experiments (DOE) to optimize process capability, throughput, yield, and operating windows, while leading technology transfer to manufacturing and contract manufacturers through comprehensive documentation and operational handoff. •    Serve as the in-house technical expert for wafer-level packaging and mechanical assembly automation equipment, including software integration and electronic hardware interfaces. •    Partner cross-functionally with design, test, reliability, and manufacturing teams to improve product manufacturability, testability, quality, and production readiness. Minimum Qualifications •    Bachelor’s degree in Physics, Mechanical Engineering, Materials Science, or a related field with 12+ years of experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience ​ •    8+ years of experience in back-end wafer processing, with expertise in materials characterization, failure analysis, IC packaging materials, and semiconductor packaging manufacturing processes. •    Experience managing overseas contract manufacturers, leading cross-functional teams to resolve manufacturing issues, and delivering consistent results in high-volume production environments. Preferred Qualifications •    Knowledge of silicon photonics