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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Digital Digital RTL Engineer

Location: San Jose, CA (Onsite)

As a Principal Engineer on our Analog/Mixed-Signal (AMS) Design team, you will architect and deliver the high-performance analog building blocks at the heart of Astera Labs' purpose-built connectivity silicon. From high-speed SerDes and PLLs to data converters and precision references, your circuits will directly enable the bandwidth, signal integrity, and power efficiency that rack-scale AI infrastructure demands.

This is a hands-on technical leadership role at a hyper-growth company defining the connectivity backbone of the AI era. You'll own designs from specification through silicon bring-up, set the technical direction for complex AMS blocks, and mentor engineers across the team — turning ambitious architecture into production-proven products that ship at scale.

• Circuit Design & Architecture

• Architect, design, and optimize high-speed analog/mixed-signal circuits such as SerDes, PLLs/clocking, ADCs/DACs, LDOs, and bias/reference blocks

• Define block-level specifications and trade-offs for performance, power, area, and yield in advanced process nodes

• Drive design methodology, reuse, and best practices across the AMS team

• Verification & Validation

• Develop and execute simulation plans across PVT, Monte Carlo, and reliability corners to ensure first-pass silicon success

• Partner with layout designers to guide floorplanning, matching, parasitics, and physical implementation

• Lead silicon bring-up, characterization, and debug, correlating measured results to models and specifications

• Technical Leadership & Collaboration

• Provide technical direction and mentorship to design engineers, elevating the capabilities of the broader team

• Collaborate cross-functionally with digital, system, product, and packaging teams to deliver integrated solutions

• Contribute to IP roadmaps, design reviews, and continuous improvement of the AMS design flow

• MS or PhD in Electrical Engineering or a related field

• 8+ years of experience in analog/mixed-signal integrated circuit design

• Proven track record designing high-speed AMS blocks (e.g., SerDes, PLLs, data converters, references/regulators) through production silicon

• Strong command of transistor-level design, device physics, and analog design fundamentals in advanced