Design Verification Manager, SSG

As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms. You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will: • Architect and implement verification environments for complex functional blocks • Create and enhance verification environments using SystemVerilog and UVM • Develop comprehensive test plans through collaboration with design engineers, SW and architects • Implement coverage measures for stimulus and corner-case scenarios • Participate in test plan and coverage reviews • Drive complex RTL and TB debugs • Drive UPF based low power verification • Contribute to verification activities across simulation and emulation platforms • Work on creating the automation scripts to support DV methodologies • Create infrastructure to performs system level performance analysis • Manage a team of 6-8 DV Engineers