AI-Driven ASIC Physical Design Principal Engineer

The application window is expected to close on: 08/07/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Collaborate with physical design teams to identify high-value automation targets: timing triage, Congestion root-cause analysis, floorplan suggestions. Evaluate and benchmark LLM-generated outputs against ground truth for Design QoR, timing impact, and sign-off compliance. Own the full developer loop: prototype → eval → production — with a focus on measurable design cycle reduction. Build agentic PnR workflows where Claude iterates autonomously on placement, routing, and timing constraints based on tool feedback loops. Create RAG pipelines that index internal PDKs, design rule documents, sign-off checklists, and runbooks for Claude to reference. Write and maintain Tcl bridge scripts that translate Claude's suggested fixes into executable EDA tool commands. Develop prompt architectures that accurately interpret STA timing reports, DRC logs, congestion maps, and power analysis outputs.

Bachelor’s degree in Engineering and 15+ years of ASIC related experience, Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience. Experience with Python and effectively leveraging AI tools through accurate prompting to enhance productivity. Experience designing and building an MCP-based wrapper layer connecting Claude to live EDA tools (Innovus, ICC2, Calibre) for real-time copilot interactions. Experience developing EDA copilots or AI-assisted design tools, along with experience in Docker and containerized EDA environments. Experience with machine learning driven placement and routing (MLPD / ML-driven PnR), and OpenAI APIs (e.g., GPT-4o, o3) and vector databases such as Pinecone or Weaviate Preferred Qualifications Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies. Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus. Why Cisco?  At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.  We are Cisco, and our power starts with you.  Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $250,600.00 to $362,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is