Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior experienced technical leader to serve as Hardware Chip Lead on our next-generation ODSP programs. What You Can Expect Chip Ownership & Program Leadership ·        Serve as the primary hardware technical owner for an ODSP chip program, responsible for tracking and driving progress across all hardware design phases from POR (Plan of Record) through MPR (Mass Production) ·        Finalize the Product Requirements Document (PRD) and bring-up requirements in collaboration with architecture, marketing, and applications engineering teams ·        Represent hardware engineering at all key program milestones: Pre-PA, PA, PSM, POR, Design Reviews, Tape-Out, and MPR ·        Coordinate and align cross-functional teams including analog design, digital design, DV, DFT, physical design, STA, firmware, validation, ATE/test engineering, product engineering, and quality ·        Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence Technical Leadership ·        Provide technical leadership for the full chip design, independently proposing and defining high-level technical solutions across the hardware stack ·        Set technical direction and drive resolution of complex, cross-disciplinary design challenges spanning analog/digital integration, high-speed SerDes, DSP datapath, and SoC architecture ·        Proactively identify technical risks early in the design cycle and drive mitigation strategies across functional teams ·        Take an active role in setting and prioritizing BU milestones and objectives; participate in architecture and design reviews at the chip and block level ·        Drive continuous improvement in design methodology, flows, and quality across the ODSP hardware organization Design & Execution ·        Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), including architecture, RTL, physical design, DFT, timing closure, and tape-out ·        Own the chip bring-up plan and execution, coordinating multi-site teams across global locations; drive Phase 0, Phase 1, and Phase 2 bring-up activities through to silicon validation ·        Oversee silicon validation, PVT characterization, ATE test program development, qualification (ESD, LU, HTOL), and production release ·        Drive resolution of post-silicon issues, coordinating debug across analog, digital, firmware, and validation teams ·        Ensure all hardware deliverables — including PRD, design documentation, and bring-up requirements — are complete and on schedule Mentorship