SOC Engineering, Sr Staff Engineer- RTL Design

Descriptions & Requirements

Job Description and Requirements

Job Title: SoC RTL Design Engineer, Sr Staff We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building and signing off RTL that actually ships in silicon, not just passes simulation. The difference between a design that tapes out clean and one that comes back with a respin is usually a clock domain crossing someone missed or a constraint someone wrote too loosely, and you are the engineer who catches those things before they become problems. You know that static checks are not checkbox exercises, they are conversations with the design, and you have learned to read what Spyglass is actually telling you beneath the noise. You have debugged enough CDC violations to know which ones matter and which ones are artifacts of tool setup. You have written enough SDC to know when a constraint is fighting the architecture instead of describing it. Running synthesis is not a handoff for you, it is part of how you validate that your RTL decisions were sound. You do not need someone to tell you what good looks like, you have a point of view on design quality and you are comfortable defending it in a review. Working across IP integration, subsystem assembly, and full SoC builds does not intimidate you. You have done it before, and you know how to move between abstraction levels without losing sight of what actually has to work in the end.

Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs Develop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff Perform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols Create and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines Collaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout The Impact You Will Have Your signoff rigor directly reduces respin risk for customers building chips in advanced nodes where a single CDC bug can cost months and millions The constraints you write become the foundation for physical implementation teams to close timing, making or breaking their ability to meet PPA targets Your synthesis validation catches architectural mismatches early, preventing costly surprises downstream in place and route The IP integrations you deliver enable startups and tier-one customers to meet aggressive tapeout schedules with confidence in design quality Your expertise in static verification tools shapes internal methodology, raising the bar for what clean RTL means across the System Solutions Group The RTL you design and integrate becomes part of production SoCs powering AI, automotive, 5G, and IoT applications in the field Your work helps Synopsys customers tape out some of the most complex and challenging semiconductor designs in the industry What You'll Need Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification