Senior ASIC Digital Design Engineer

Basic Qualifications Education Requirements: Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.

Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.

If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development — on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.

The right candidate has worked in larger, structured design environments where verification is a discipline in its own right — with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.

- Own RTL design tasks — Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification - Contribute to timing closure — Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes - Support verification efforts — Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures - Participate in JIRA triage — Review incoming issues and help maintain an accurate and actionable backlog - Participate in code reviews — Engage in RTL code reviews, providing and receiving constructive technical feedback - Support program planning — Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting - Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks - Support technology evaluation — Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling - Collaborate broadly — Participate in Integrated Product Teams and working groups

- 5–8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer - Experience working in larger, structured design teams with formal verification processes and independent verification partners — not solely in small-team or solo development environments - Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review — not through iteration on hardware - Some experience contributing to ASIC tape-out efforts is a plus - Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator - Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent) - Working knowledge of: - RTL design and microarchitecture - Bus fabric design and verification - Clock