Principal Technical Engineer 3rd Party IP Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Principal Technical Engineer 3rd Party IP Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Storage, Security, and Networking. You’ll be part of the 3rd party IP management team. In this role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and, in this position, you will engage all parts of Marvell. What You Can Expect Looking for a talented 3 rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients . Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, hyper-scaler, communications, and storage. As a 3 rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development , technology compliance, core integration, test compliance and silicon validation.   You will assist sales in winning bids by working with leading edge IP providers to meet customer requirements. You will manage 3rd party developers in completing core designs and providing required design rules. You will advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider. Post-silicon validation at customer sites will require a limited degree of travel. Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution. You will assist with 8D follow-through for significant supplier issues.

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or e quivalent professional experience in lieu of a formal degree Proficient in u nderstanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging Proficient in project management tasks required to manage 3 rd party developers Broad - based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking   Good u nderstanding of Design - F or - Test concepts including DFT logic insertion, test generation, scan and embedded core testing   Good communication and customer management skills   Expected Base Pay Range (USD) 152,300 - 225,440, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at