Physical Design Engineer, Staff

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in physical design and timing closure, and you know that the difference between a chip that tapes out clean and one that comes back with yield issues is usually a decision made during floorplanning or a timing corner someone didn't validate hard enough. You are the engineer who catches those decisions before they become expensive problems. Working across advanced nodes like 5nm, 3nm, and beyond doesn't intimidate you because you have been there, debugged the DRC violations at 2am, closed timing on a block everyone said was impossible, and learned what actually matters versus what just looks good in a review slide. You do not wait for perfect specs. When the RTL drops and the constraints are half-baked, you start asking the right questions, build your SDC from first principles, and move forward. At Synopsys, you will work on silicon lifecycle monitors that actually ship in automotive and consumer products.

Design and implement RTL to GDS flows for on-chip silicon lifecycle monitors including process, voltage, temperature, glitch, and droop sensors Own digital backend from synthesis through tapeout: floorplanning, power planning, multivoltage design with UPF and VCLP, placement, CTS, and routing Develop and close pre-layout and post-layout STA across multiple corners using PrimeTime and PrimeTime PX, including SDC creation and timing ECO generation Execute physical verification and signoff: DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff using ICV and RedHawk Build and refine design flows in collaboration with architecture and circuit teams, scripting automation in TCL and Perl Generate timing and DRV ECOs for closure, working iteratively to meet PPA targets on advanced FinFET and GAA nodes The Impact You Will Have Enable next-generation intelligent sensors that monitor silicon health in real time, improving product reliability in automotive and consumer markets Drive tapeout success on advanced nodes by delivering clean, timing-closed designs that meet aggressive PPA and yield targets Build reusable methodologies that accelerate physical design execution across multiple product teams at Synopsys Reduce risk and schedule slip by catching design issues early through rigorous analysis and signoff discipline Contribute to the differentiation of Synopsys IP products by embedding best-in-class physical design practices Influence tooling and flow improvements that benefit the broader Synopsys design community What You'll Need Bachelor's or Master's in Electrical Engineering with 5+ years in physical design, physical verification, and STA at IP, block, or full-chip level Proven tapeout success on advanced nodes: 14nm, 10nm, 7nm, 5nm, 3nm, or 2nm Strong experience with DRC, LVS, DFM cleaning, and generating ECOs for DRV and timing closure Proficiency with Synopsys tools: Fusion Compiler, VCLP, PrimeTime, PrimeTime PX, ICV, and RedHawk Solid understanding of multivoltage design, UPF, SDC constraints, OCV, POCV, derates, and crosstalk Experience scripting in TCL and Perl to automate flows and customize methodologies Who You Are You can spot a floorplan that will fail timing in two weeks and explain exactly why in terms the team can act on immediately Detail-oriented enough to catch a single missing mode in an SDC file, but pragmatic enough to know when a 2ps margin is good enough Comfortable working independently to debug a tricky LVS issue, but quick to pull in the right people when the