Physical Design Engineer

Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field. We are looking for a motivated and detail-oriented Physical Design Engineer to join our ASIC Physical Design team. You will work alongside senior engineers to implement and verify complex digital designs from netlist to GDSII, gaining hands-on experience across the full backend flow on cutting-edge FinFET process technologies. TSMC N5 / N4P / N3 Python • TCL Agentic AI Flow Development What You'll Do Support floorplanning, placement, clock tree synthesis (CTS), and routing under guidance of senior PD engineers Assist in timing closure activities including basic STA analysis, path debugging, and constraint verification Run and analyze IR drop, signal integrity, and electromigration reports using standard EDA tools Execute physical verification flows (DRC, LVS, DFM) and triage violations Develop and maintain Python and TCL scripts to automate repetitive tasks (report parsing, constraint generation, batch runs) Contribute to flow development initiatives — help build and document in-house PD automation scripts and runsets Explore Agentic AI-assisted design tools for automated constraint checking, violation triage, and design space exploration under mentor guidance Collaborate with front-end, DFT, and verification teams on design handoffs and ECO implementation What You'll Need B.Sc. in Electrical Engineering, Computer Engineering, or equivalent 0–3 years of experience in digital Physical Design (academic projects or internships count) Basic understanding of floorplanning, PnR, CTS, and STA concepts Familiarity with at least one EDA tool: Synopsys ICC2, Cadence Innovus, Calibre, or PrimeTime Scripting exposure in Python or TCL — ability to read, modify, and write scripts Eagerness to learn advanced process nodes (TSMC N5/N4P/N3/FinFET) Good analytical and problem-solving skills Nice to Have Exposure to TSMC advanced node design rules Familiarity with DFT concepts (scan, ATPG) Any coursework or project experience with AI/ML tools applied to EDA or flow automation *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security