Principal Digital Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Digital Design Engineer

Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.

As AI workloads continue to scale, Astera Labs is developing innovative connectivity products that deliver industry-leading performance, reliability, and scalability. We are looking for an experienced Digital Design Engineer to join our Silicon Engineering team and help architect and build the next generation of connectivity solutions.

We are seeking a Principal Digital Design Engineer with deep expertise in RTL design, microarchitecture, and high-performance SoC development. In this role, you will lead the architecture and implementation of complex digital subsystems for cutting-edge AI infrastructure products.

You will collaborate closely with Architecture, Verification, Physical Design, Firmware, Validation, and Product Engineering teams to deliver high-quality silicon while driving technical excellence across multiple programs.

Architecture & Design

• Drive the microarchitecture and RTL implementation of complex digital IPs and SoC subsystems.

• Translate architectural specifications into efficient, high-quality RTL designs.

• Define scalable and reusable architectures for high-performance silicon products.

• Optimize designs for performance, power, area (PPA), reliability, and testability.

• Participate in architecture reviews and influence key technical decisions.

RTL Development

• Design and implement synthesizable RTL using Verilog/SystemVerilog.

• Develop high-speed datapaths, control logic, arbitration schemes, finite state machines, and protocol engines.

• Ensure RTL quality through comprehensive design reviews, linting, CDC/RDC analysis, and synthesis validation.

• Support design closure throughout the development lifecycle.

Protocol & Connectivity Design

Lead or contribute to the design of IPs supporting:

• Compute Express Link (CXL)

• PCI Express (PCIe Gen4/Gen5/Gen6)

• Ethernet (10G–800G)

• High-speed SerDes interfaces

• AXI, APB, and AHB interconnects

• Memory subsystems and coherent