Senior Manager - System Validation
AMD
- Location
- Bangalore, India
- Employment
- Full Time
- Work model
- On-Site
- Level
- Senior
About this role
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
We are looking for a Senior Manager to lead System Validation for BIOS, Firmware and Driver validation activities across our embedded product portfolio. This role will provide hands-on technical leadership, drive validation coverage, strengthen test planning and execution discipline, and ensure timely visibility to critical issues, risks and customer-impacting defects. The leader will work closely with development, silicon IP enablement, silicon validation, platform and customer-facing teams to ensure validation readiness, reduce test escapes and improve engineering effectiveness through scale and AI-driven initiatives. THE PERSON A strong technical validation leader with deep understanding of system-level validation across BIOS, firmware, drivers and platform software stacks. Demonstrates ownership in defining validation coverage, test strategy, execution governance and defect triage for complex silicon and platform programs. Builds trusted networks across client and server ecosystems, development teams, silicon IP enablement teams and validation organizations to improve end-to-end product readiness. Balances technical depth with people leadership, helping the team grow in capability, execution maturity, collaboration and customer orientation. Brings a continuous improvement mindset with the ability to drive scale, automation, traceability and AI-enabled productivity across validation workflows.
KEY RESPONSIBILITIES
Provide technical leadership for system validation activities covering BIOS, firmware and driver validation across assigned embedded programs. Define and drive the right validation coverage by partnering with architecture, development, silicon IP enablement, silicon validation, platform and customer enablement teams. Own test management discipline including validation planning, test readiness, execution tracking, completion governance and timely reporting of progress, gaps and risks. Drive first-level triage for critical issues by ensuring structured debug data collection, clear ownership alignment, prioritization and timely handoff to the appropriate development teams. Establish strong collaboration forums with BIOS, firmware, driver, silicon IP, silicon validation and platform teams to close coverage gaps and improve defect discovery earlier in the lifecycle. Build and maintain technical connects in the client and server spaces from which the group leverages devices, ecosystems, validation methodologies and learnings. Reduce validation escapes through improved test strategy, coverage analysis, defect trend reviews, regression rigor and disciplined exit criteria. Support customer escalations and critical field issue triage as required, ensuring responsiveness, technical clarity and coordinated execution across engineering owners. Lead team development by coaching engineers and leads, improving technical depth, strengthening ownership behaviors and building succession for key validation areas. Drive scale initiatives across validation execution, including automation, reusable test assets, consistent dashboards, traceability from requirements to tests, and execution efficiency improvements. Champion AI initiatives that improve test planning, coverage mapping,