Lead Engineer/ Staff – RISCV Subsystem RTL Design

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Area Engineering - IP Design Location:  Bangalore Educational Requirements Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics Job Description Own micro-architecture, RTL design, integration, and delivery of RISC‑V subsystem components for next-generation SoCs targeting mobile, automotive, AI, compute, and connectivity platforms. The subsystem includes control CPUs, interrupt management, security, power management, debug, and system infrastructure blocks.

Work with architecture, software, verification, and SoC teams to define requirements, interfaces, memory maps, interrupt architecture, power features, and subsystem integration strategies. Develop scalable micro-architecture specifications optimized for performance, power, area, safety, and product-specific use cases across multiple SoC programs. Implement high-quality RTL using Verilog/SystemVerilog and drive design convergence through lint, CDC/RDC, synthesis, power intent, DFT, and formal verification checks. Collaborate with firmware, verification, and integration teams to enable subsystem bring-up, feature validation, performance tuning, and seamless deployment into complex SoC environments. Debug and resolve functional, integration, timing, power, and silicon issues using simulation, waveform analysis, emulation, and post-silicon debug techniques. Drive technical reviews, mentor junior engineers, contribute to subsystem roadmap planning, and coordinate execution across globally distributed cross-functional teams. Required Skillset Strong VLSI digital design experience with expertise in micro-architecture development and RTL implementation. Good understanding of RISC‑V architecture, interrupt handling, memory management concepts, power management, debug infrastructure, and system-level design principles. Knowledge of on-chip interconnect protocols such as AXI, AHB, APB, ACE, CHI, or equivalent high-performance SoC fabrics. Strong debugging, analytical, and problem-solving skills with the ability to root-cause complex hardware and integration issues. Good understanding of ASIC development flow including architecture, RTL design, synthesis, timing closure, verification, and silicon bring-up. Effective communication and collaboration skills to work across architecture, software, verification, physical design, and SoC teams. Desired Skillset Experience with low-power design techniques including clock gating, power collapse, retention, isolation, voltage domains, and UPF-based design methodologies. Familiarity with interrupt architectures such as RISC‑V AIA/APLIC/IMSIC, system control processors, safety mechanisms, and subsystem infrastructure IPs. Proficiency in scripting languages such as Python, Perl, or Tcl for automation, flow development, and productivity improvements. Working knowledge of synthesis, DFT, CDC/RDC, formal verification, assertions, performance analysis, and system-level modeling. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will