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Packaging Engineer

AMD

Hsinchu, TaiwanFull TimeSenior
Sign in to applyVerified 1h ago
Location
Hsinchu, Taiwan
Employment
Full Time
Work model
On-Site
Level
Senior

About this role

WHAT YOU DO AT AMD CHANGES EVERYTHING   At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.   Together, we advance your career.

THE ROLE

Candidate is required to work closely with oSATs and cross-functional teams to bring up and sustain for InFO, EFB/CoWoS-L,CoWoS-S, WLFO, FCBGA, LGA and chiplet packages.   THE PERSON: The ideal candidate will have a balanced mix of strong technical knowledge as well as program management experience in InFO, EFB/CoWoS-L,CoWoS-S, WLFO, FCBGA, LGA and chiplet package functions.   The successful candidate must be a team player with a commitment to meeting deadlines. Lead & drive for solutions with an aptitude to thrive in a fast-paced multi-tasking environment. He or she would have excellent cross functional project management skill, with strong interpersonal skills and good communication & presentation skills. He or she must have good command of both written and spoken English.

KEY RESPONSIBILITIES

Responsible for InFO, WFB/CoWoS-L, CoWoS, WLFO, FCBGA, LGA and Chiplet package Manufacturing readiness for New Product bring up at manufacturing site. Responsible for packaging yield, quality, cost and operation productivity improvements and sustaining activities. Drive assembly process baseline standardization and continuous improvement. Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack. Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products Co-work with Packaging BU on NPI and Ramp Up readiness at manufacturing site. Proactively follow up task assignments and report status timely to stakeholders. Responsible to manage performance of assembly manufacturing site/supplier regarding yield & quality, out of control lot disposition, and any outliers with close loop on reporting. The role will require working together with both internal engineering counterparts & extensive interactions within the Package engineering organization, and interacting with several other internal organizations (procurement, supply chain, reliability, etc.) on program deliverables with accurate and timely reporting of program status with executive summary update throughout its life cycle. Responsible for strategic supplier management. Plan and execute change management from internal or external parties. Assist in additional duties as deemed fit by supervisor. Job may include other duties as assigned/ deemed fit by supervisor.

PREFERRED EXPERIENCE

Experience in InFO or 2.5D/3D Bump/TSV/Packaging, Flip Chip BGA/LGA or WLFO process engineering with min total 7 years assembly work experience. Possess InFO, Chiplet packaging, 2.5D/3D TSV/Packaging, Flip Chip BGA/LGA process knowledge and Chip-Packaging Interaction knowledge. Lead and manage team experience. Strategic supplier management experience. Familiar with DOE and JMP. MS degree in Mechanical or Material or Chemical Engineering. Creative, highly motivated self-driven individual team player with the demonstrated ability to independently complete complex engineering tasks on/ahead of time/Lead & Drive for solutions and an aptitude to thrive in a fast-paced multi-tasking environment. Experience is Preparing reports /Presentation and ability to communicate Root cause and Resolution effectively.

Packaging Engineer at AMD, Hsinchu, Taiwan | Yoinka