Senior System Software Engineer, SoC Power and Performance - O-RAN Infrastructure
NVIDIA
- Location
- US CA Santa Clara
- Work model
- On-Site
- Level
- Senior
- H-1B history
- 394 approvals (FY2023)
- Posted
- 1d ago
Skills
About this role
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are looking for a highly motivated Senior System Software Engineer to develop and improve system software for next-generation O-RAN infrastructure. You will work at the intersection of SoC architecture, cellular systems, firmware, operating systems, and radio-access-network workloads, helping deliver industry-leading performance and energy efficiency. This role focuses on software for 5G and emerging 6G infrastructure, including Radio Units (RUs), Distributed Units (DUs), and the interfaces connecting them. You will collaborate with hardware, architecture, platform, networking, and cellular-software teams throughout pre-silicon development, silicon bring-up, productization, and deployment. What you’ll be doing: Design, develop, test, and optimize system software and firmware for SoCs used in O-RAN and cellular infrastructure. Develop power-management policies and performance optimizations across CPU, GPU, accelerator, memory, interconnect, I/O, and networking subsystems. Analyze representative RU and DU workloads to identify architectural and system-level bottlenecks, including compute, memory bandwidth, latency, synchronization, and data-movement constraints. Develop and tune power-management capabilities such as dynamic voltage and frequency scaling, clock and power gating, idle-state management, thermal controls, and system-level power budgeting. Create performance and power models, measurement tools, benchmarks, and automated test infrastructure for both pre-silicon and post-silicon environments. Use simulation, emulation, prototyping, and production silicon to validate architectural decisions and identify power and performance issues. Evaluate system behavior against O-RAN and cellular-interface requirements, including timing, synchronization, latency, throughput, and reliability. Influence future SoC, platform, and cellular-software architectures based on workload analysis and measurements from deployed systems. What we need to see: Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience. 5+ years of relevant experience in system software, embedded software, firmware, computer architecture, cellular infrastructure, or performance engineering. Demonstrated experience developing and debugging software for complex SoCs or embedded platforms. Strong programming skills in C or C++, along with proficiency in Python or a comparable scripting language. Strong understanding of computer architecture and hardware-software interaction, including multicore systems, memory hierarchies, caches, interconnects, interrupts, memory-mapped I/O, and DMA. Experience with operating-system internals, Linux kernel development, device drivers, concurrency, virtual memory, and real-time or latency-sensitive programming. Hands-on expertise in performance measurement, workload characterization, data analysis, bottleneck identification, and system optimization. Working knowledge of SoC power-management concepts, including DVFS, clock and power gating, thermal management, and power/performance budgeting. A strong grasp of cellular infrastructure and radio-access-network architecture is expected. Required knowledge of interface standards relevant to