Senior DFT Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are looking for a highly motivated Senior DFT Engineer to join our Silicon Engineering team. In this role, you will be responsible for architecting, implementing, and validating Design-for-Test (DFT) solutions for complex SoCs. You will work closely with RTL, Physical Design, ATPG, Verification, and Product Engineering teams to ensure high manufacturing test coverage, quality, and silicon reliability.

• Develop and implement DFT architecture for complex SoCs, including Scan, MBIST, Boundary Scan (JTAG), and Compression techniques.

• Integrate DFT logic into RTL while ensuring minimal impact on design performance, power, and area.

• Execute scan insertion, DFT synthesis, and DFT rule checks (DRC).

• Generate and validate ATPG patterns for stuck-at, transition, path delay, and bridge fault models.

• Analyze test coverage reports and drive improvements to achieve production-quality coverage.

• Perform gate-level simulations and debug DFT-related issues throughout the design cycle.

• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams during implementation and silicon bring-up.

• Support silicon validation, failure analysis, yield improvement, and manufacturing test optimization.

• Develop and maintain DFT methodologies, automation scripts, and best practices.

• Participate in design reviews and provide technical guidance on DFT implementation.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

• 3–6 years of hands-on experience in Design for Test (DFT) for ASIC/SoC development.

• Strong understanding of digital design fundamentals and ASIC design flow.

• Experience implementing Scan, MBIST, JTAG/IEEE 1149.1, Compression, and ATPG methodologies.

• Hands-on experience with DFT insertion, ATPG generation, and coverage analysis.

• Strong debugging skills and understanding of gate-level simulations.

• Good knowledge of timing, synthesis, and low-power design concepts.

• Excellent analytical, problem-solving, and communication skills.

Preferred Technical Skills

• Experience with industry-standard EDA tools such as:

• Siemens Tessent

• Synopsys TestMAX / DFT Compiler

• Cadence Modus

• Knowledge of ATPG fault models including Stuck-at, Transition, Path Delay, Cell-aware, and Bridge faults.

• Familiarity with IJTAG (IEEE 1687), LBIST, OCC,