Sr Staff Engineer, Formal Verification

Senior Staff Formal Verification Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not. You understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not. Mentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters.

Build and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a corner Create formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on those behaviors Guide design and verification engineers on effective use of formal tools, reviewing setups and proofs to catch issues before they become blockers Maintain and extend assertion libraries that work for both simulation and formal contexts, ensuring consistency across verification approaches Apply formal techniques like bounded model checking, induction, and abstraction to prove correctness of complex RTL designs Debug RTL when proofs fail, tracing back from a counterexample to the root cause in the design or the verification environment Train team members and mentor junior engineers on formal methods, assertion-based verification, and debugging strategies The Impact You Will Have Catch design bugs that simulation would miss, preventing costly respins and schedule slips downstream Raise the quality bar for digital designs across Synopsys products by making formal verification a standard part of the process, not an afterthought Accelerate verification closure by proving corner cases formally instead of writing thousands of directed tests hoping to hit them Build verification infrastructure that other engineers can use effectively, multiplying your impact across the team Improve design quality at the source by working closely with RTL designers to identify and fix issues early Contribute to the silicon and IP solutions that power everything from AI accelerators to automotive systems Strengthen the formal verification capability of the Bangalore team through knowledge sharing and hands-on mentorship What You'll Need 8+ years of industry experience