Senior VLSI Library Methodology Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Are you excited to architect and build the automation infrastructure behind next-generation silicon design? We’re seeking a Senior VLSI Library Methodology Engineer to join our team and drive the development, specification, and implementation of scalable systems. These systems support library analysis, quality validation, documentation, and deployment for NVIDIA’s Physical Design flows. In this role, you will help build robust, data-driven automation and verification infrastructure. You will collaborate with methodology, library, and build teams to improve quality, efficiency, and scalability on advanced nodes.

Architect, specify, and implement scalable automation systems for examining, verifying, issue checking, reporting, and release readiness across GPU and SoC flows Build and enhance end-to-end infrastructure, from analysis pipelines and regression frameworks to dashboards and reporting systems, with strong focus on usability, maintainability, and scale Develop automated library analysis, validation, and quality control flows using modern scripting and EDA tools, including consideration of runtime, capacity, and resource efficiency for large-scale analysis Collaborate with design, CAD, and library teams to integrate quality systems and improve cell design methodologies, applying adaptive threshold partitioning Define and implement methodologies for issue triage, data integrity, quality metrics, and release criteria that improve visibility and decision-making across the flow What we need to see: M.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience) 4+ years of experience in library methodology, physical design, CAD, design automation, or related VLSI infrastructure development Strong software development skills in Python, C++, or Perl, with hands-on experience building workflow automation, data pipelines, validation frameworks, and reporting/dashboard systems Experience designing and implementing production-quality technical systems from an architectural and implementation point of view, including specification, scalability, and operational robustness Hands-on experience with industry-standard EDA tools such as Innovus, Fusion Compiler, Crosscheck, Virtuoso, or similar, including scripting, customization, or tool integration Ways to stand out from the crowd: Understanding of how library models are consumed in chip design flows, including synthesis, place and route, timing closure, and power analysis Experience building robust quality systems for library modeling, validation, or physical design automation, including exposure to contextual model calibration Background in designing infrastructure that tracks critical metrics such as validation pass rates, regression health, issue trends, release readiness, and resource utilization Experience balancing analysis quality with runtime, compute capacity, and infrastructure efficiency in large-scale automation environments Applied AI/ML/LLM experience to improve EDA workflows, automation systems, or design methodologies We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of