Sr. Manager ASIC, Annapurna Labs - Cloud Scale Machine Learning Acceleration Team

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Key job responsibilities - Lead and grow a team of SOC integration engineers responsible for critical deliverables in our ML accelerator chips - Drive technical decisions across multiple disciplines (RTL, timing, DFT, physical design) - Ensure on-time delivery of complex SOC integration milestones - Establish and maintain best practices for top-level integration, including clock/reset architecture, CDC methodology, and quality metrics - Interface with various stakeholders including architecture, verification, and physical design teams You will thrive in this role if you: - Have a proven track record leading SOC integration teams through successful tape-outs - Excel at cross-functional leadership and can drive complex technical decisions across multiple teams - Are passionate about developing engineers and implementing robust integration methodologies - Have deep expertise in high-performance SOC design, including clock/reset architecture, timing closure, and CDC methodology - Are data-driven and can effectively balance technical excellence with project execution About the team Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.