CPU RTL Design Engineer (Senior/Staff) - Cambridge, UK

Company: Qualcomm Technologies International Ltd Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture and also help with architecture/product definition through early involvement in the product life cycle. Where you will be working Cambridge, located in the East of England, 50 miles north of London, is a unique and beautiful city, renowned for its world-class university and the thriving cluster of high technology businesses that have grown up around it.  Cambridge is well served by road and rail links, and is within easy distance of the major London airports Cambridge is our largest office in the UK, with team members including engineers, business strategists and support staff Roles And Responsibilities will include Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po   What are we looking for Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python What's on Offer Apart from working in an open, relaxed and collaborative space, you will enjoy: Salary, stock and performance related bonus Maternity/Paternity Leave Employee stock purchase scheme Matching pension scheme Education Assistance Relocation and immigration support (if needed) Life, Medical, Income and Travel Insurance Subsidised memberships for physical and mental well-being Bicycle purchase scheme Employee run clubs, including, running, football, chess, badminton + many more Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered,