DFT Staff Engineer- SoC Engineering

Job Title: DFT Staff Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are a hands-on DFT expert who has driven test architecture and implementation for complex SoCs that tape out and succeed in production, not just in reviews. You understand how decisions made around RTL freeze impact coverage, yield, and test cost at volume, and you can confidently define the right strategy across scan/ATPG, MBIST/LBIST, and broader test hooks needed for bring-up and failure analysis. You do not just run tools. You understand the engineering tradeoffs between test time, area/power overhead, and coverage, and you can explain and defend why a specific approach is right for a given subsystem and product context. Operating with high autonomy, you own technically complex deliverables end-to-end and influence outcomes through deep expertise and strong cross-functional collaboration. When you spot untestable logic or weak test hooks, you propose practical fixes that teams actually adopt. You are comfortable leading technical discussions with architects and pushing back when decisions introduce coverage gaps or yield risk, because you have seen what happens when those issues reach production.

Own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout, working directly with customer and internal design teams Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, quality, yield, and cost targets Drive DFT signoff readiness by identifying testability risks early, proposing design changes, and ensuring closure across the RTL-to-GDS flow Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools to solve real customer problems on active service projects Partner with silicon validation and test engineering teams on post-silicon debug, failure analysis triage, and pattern refinement to improve production outcomes Collaborate closely with RTL design, functional verification, physical design, timing, and power teams to ensure testability is designed in from architecture through signoff Provide technical guidance to peers through design reviews, integration/debug support, and best-practice sharing The Impact You Will Have Enable first-pass silicon success by surfacing and resolving DFT issues before tapeout Improve test coverage and yield through robust scan/ATPG and BIST strategies aligned to product constraints Reduce production test time and cost for SoCs in high-performance computing, automotive, and aerospace domains Create reusable DFT methodologies that scale across multiple programs and customer engagements Strengthen customer confidence by delivering DFT solutions that work in production, not just in simulation Influence Synopsys tools and IP direction by feeding back real project learnings and customer pain points Accelerate tapeout schedules by catching testability gaps early and proposing fixes teams can implement without rework What You'll Need Bachelor's or Master's degree in Electronics Engineering,