Staff Test Engineer, Hardware Security

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The Staff Test Engineer in Hardware Security and OTP (One-Time Programmable) Programming is responsible for leading a team of engineers in the development, implementation, and optimization of security testing and programming solutions for ASIC (Application-Specific Integrated Circuit), SoC (System on Chip), and multi-chiplet devices. This role requires a deep understanding of manufacturing hardware security principles, test methodologies, and programming techniques to ensure the security, integrity, and reliability of semiconductor products.

Lead and mentor a team of hardware security test engineers, providing guidance and support in project execution and professional development. Foster a collaborative and innovative team environment, encouraging knowledge sharing and continuous improvement. Manage multiple projects simultaneously, ensuring timely delivery of high-quality test and programming solutions. Coordinate with cross-functional teams to align project objectives and deliverables with overall business goals. Working with cross functional teams (Design, DFT, Design Verification, Software, Program Management, Product Engineers, and IP-level test engineers) to create test plans prior to chip tape out in accordance with the product’s lifecycle state (LCS) and HW/SW/DFT accessibility requirements. Work in a fast-paced environment to bring up silicon solutions for both internal and external customers. Work on ATE (93K and UF+) platforms to develop test programs in Java and VB that are scalable and tested extensively before deploying to production. Analyze test results and provide actionable insights to improve yield, reduce test time, avoid fusing errors, ensure product security and performance. Drive debug efforts to solve chip fusing functionality and yield issues. Develop advanced validation solutions and tools using SW systems and applications. Design custom digital circuitry to support on-board boot and other product-specific security requirements.

English fluent (>95% verbal and written). 2+ years of experience with security HW architecture/design/validation/test related areas of silicon solutions. Familiarity with basic test methodologies including Boundary Scan, ATPG, MBIST and test protocols such as TIC and JTAG. Experience with SW/HW debug tools. Experience with Lauterbach Trace32 preferred. Embedded SW development / FPGA programming is a plus. Experience with PCB schematic capture and layout.

BS. B.Eng. in Computer Engineering, Computer Science, Electrical Engineering, or related fields. 2+ years of experience in leading/managing engineering teams. Must be able to plan and execute an ATE test program from start to finish, on time, under a tight test time budget, while also innovating to help our global team excel. Must work well in a team environment but also be self-driven to complete tasks without supervision. Fusing is a destructive process, so attention to detail is a must. Attention to detail. Ability to multitask and prioritize effectively. Strong verbal communication skills, ability to collaborate with many teams to gather requirements and debug issues. 3+ years of relevant experience in ATE and test methodologies. Experience with Advantest 93K preferred. Experienced in Object Oriented Programming (OOP) languages (Java, C++). Able to write Java code for basic ATE functionality/measurements. Proficient with Unix/Linux. Scripting experience with Perl/Python preferred. Experience with SVN/GIT or other version control solutions. Strong SW systems and applications development background. Experience with digital circuit design. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or