Network Interface Controller (NIC) Architect

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Overview We are seeking a highly experienced Network Systems Architect to lead the design and development of our next-generation high-performance NICs. In this role, you will define end-to-end hardware and software architectures tailored for AI networking, guiding products from conceptualization and customer requirements through implementation and system verification. You will play a critical role in influencing product strategy, ecosystem engagement, and industry specifications.

Define end-to-end hardware/software architectures for Remote Direct Memory Access (RDMA), Ultra Ethernet, RDMA over Converged Ethernet (RoCE), and multipath transport. Architect NIC datapaths, offloads, programmable congestion control, load balancing, and multiplane networking. Translate customer, product, and standards requirements into implementable architectures using executable modeling, workload analysis, and silicon-aware tradeoffs. Design and evaluate queue, buffer, and telemetry systems, ensuring memory architectures meet target workloads without requiring post-silicon corrections. Interface with programmable logic team help define APIs and trade-offs between different solutions Decompose collective-communication libraries (such as NCCL and RCCL) to derive minimum NIC primitives, feature dimensions, and hardware-software interfaces. Act as a technical interface to strategic customers to help define solutions. Drive multi-vendor convergence and standards development, participating in organizations like the Ultra Ethernet Consortium or Open Compute Project. Influence product strategy, technical roadmaps, and cross-organizational engineering teams without direct management authority. Core Requirements Education: MS or Ph.D. in Engineering, Computing, or a closely related discipline.

16+ years of dedicated experience in high-performance Network Interface Controller (NIC) and network-system architecture. Protocol Expertise: Deep understanding of RDMA transports, congestion control algorithms, dynamic connection management, and multipath packet spraying. Hardware/Software Co-Design: Extensive background in FPGA/ASIC systems, direct memory access, and defining firmware/driver interfaces. Leadership: Proven track record of cross-organizational decision-making and guiding hardware, software, firmware, and verification engineers through implementation. Active participation or leadership in network standardization bodies (e.g., Ultra Ethernet Transport Software Working Group). Experience defining composable hardware/software plug-in architectures or programmable packet-processing pipelines. A strong portfolio of issued patents, academic publications, or technical reports related to network systems.

The annual base salary range for this position is USD 200,000.00 To USD 320,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship,