SoC Verification- Principal Engineer

Descriptions & Requirements

Job Description and Requirements

Alternate Job Title: SoC Verification- Principal Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of SoC verification, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a verification plan you wrote in week two. You know that verification is not just about coverage numbers, it is about understanding what can actually break in silicon and making sure it does not. Leading a team does not mean delegating and disappearing. You are in the waveform debugger alongside your engineers when a protocol violation shows up at 2am, and you can spot a gap in a testbench architecture during a design review without needing to see the code. You have learned to read a customer's SoC spec and immediately know where the risk lives, whether it is in the interconnect, the power domain crossings, or that custom accelerator block nobody wants to talk about yet. You do not wait for perfect requirements. You ask the right questions, build a verification plan that actually maps to what can go wrong, and adjust as the design evolves. At Synopsys, you will work directly with customers building chips for AI, automotive, aerospace, and high-performance computing, and the verification strategies you build will determine whether their silicon works.

Lead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables Lead verification teams of 3-4 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios Develop verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve Integrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments Debug complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams Identify project risks early, propose mitigation strategies, and communicate status and blockers to Synopsys management and customer stakeholders Drive methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption The Impact You Will Have Your verification plans and execution will directly determine whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems The engineers you mentor will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements Your early identification of design risks and verification gaps will prevent costly respins and post-silicon surprises for customers building chips in 5nm and below The methodology improvements you drive will reduce verification cycle time and improve coverage quality across dozens of SSG projects annually Your direct customer engagement will shape how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows The testbench architectures and VIP integration strategies you build will become reusable assets for future projects, compressing ramp time for new